Why does Chord use FPGAs and discrete conversion instead of DAC chips or a custom ASIC?

The short version

Watts frames the choice as two separate decisions: do the digital processing in an FPGA rather than in a DAC chip's built-in filter, and do the digital-to-analog conversion with discrete parts rather than on silicon. In December 2022 he wrote that "all my DACs have separate devices for the digital and analogue parts" Head-Fi, Dec 2022. In 2017 he put his commitment flatly: the best sound "is only achievable with FPGA’s and discrete DAC’s" article, Dec 2017.

Where he says this comes from

He bases the argument on his own work designing chips for semiconductor companies, which he says ran for 14 years article, Dec 2017audio-2G 1:20. In 2016 he said the DSD DACs he was making in the early 1990s, before pulse array, were "a nightmare from a consistency point of view", and that "the only way of solving these issues was to take control over every element within a DAC" Head-Fi, Jun 2016. In 2022 he tied the move to FPGAs to what he had learned on the Deltec PDM1024 DAC article, Mar 2022. He has given different start dates for his FPGA work: the mid-1990s in 2014 Head-Fi, Apr 2014, "I started using them in 92" in 2023 Soundnews 17:11, and 1995 in a video published August 2024 (recording date not stated) Audiophilesdoteu 3. He dates the invention of pulse array, his discrete conversion method, to 1995 Head-Fi, Dec 2017Pursuit Perfect System 14:00.

Reason 1: economics and design freedom (2014 to 2026)

In April 2014 he explained the trade-off: chip design has "very high initial cost", while an FPGA has higher cost per device but, ignoring design effort, "the up front charges are nothing"; "For custom silicon devices, you have to sell millions to get your money back" Head-Fi, Apr 2014. Of the original Hugo he said "There is no way the complexity that goes into Hugo would make it into a custom chip, the volumes are too small" Head-Fi, Apr 2014. In 2015 he added that chip teams design to a marketing spec and stop there: "No one does any listening tests, it is all done on straight forward measurements" article, Apr 2015.

He has told one story several times: a chip project where $10 million had been spent and the die had to lose five cents of cost, which he says took nine months Upscale Audio 1:39The Source AV 6:15HiFi Buys 29:15. In 2023 he contrasted that with FPGA work: "With FPGA design, you can do what the hell you like" The Source AV 6:15. In an interview recorded at a Munich show, most likely May 2024 (date unconfirmed; published February 2025), he said that with an FPGA, "if you want more complexity, you buy a bigger FPGA or you use multiple FPGAs" audio-2G 2:58. In 2026 he gave internal word length as an example: "So if I want 192 bits internal accuracy, I can do that with an FPGA" Audio Force 2:28.

Reason 2: processing capacity for the interpolation filter

He ties the FPGA directly to the WTA filter's tap counts. In July 2014 he said conventional ASIC DACs generally have a single 12 MHz DSP core, while "Hugo has 16 cores running at 208 MHz" Head-Fi, Jul 2014. He has said Mojo has 44 DSP cores and DAVE 166 running Head-Fi, Aug 2016; for the M scaler he gave 528 processors working together Head-Fi, Jul 2018Hifistatement 0, on an FPGA he said has 740 DSP cores Hifistatement 0miceblue425 45:09. He has claimed Mojo has 500 times the processing of conventional chips (2016) and Mojo 2 "over 500 times more processing power than a regular chip DAC" (2022) What Hi-Fi? 4:16MFG Audio Reviews 22:49. In 2023 he cited "the popular ESS9038 Pro chip for example has only 128 taps", which he called "plain inadequate for transient timing reconstruction, but plenty of scope for messing around with the sound" Head-Fi, Sep 2023. In that August 2024 video (recording date not stated) he summed up that the WTA approach needs both the algorithm and "a lot of computing capacity with which we get with the appropriate sized FPGA" Audiophilesdoteu 5:27.

He also argued against using a PC or microprocessor instead: an FPGA does each FIR tap's operations "in parallel at once", where a processor works in sequence (2016, 2017) Head-Fi, Aug 2016miceblue425 46:01. In December 2019 he said the M Scaler's roughly 12 W of processing is "the huge benefit of doing it within an FPGA rather than a PC, which would need orders of magnitude more power and so more noise" Head-Fi, Dec 2019. In 2017 he said a GPU route would mean a product for dedicated users rather than one bought in a shop, and that a pocket M Scaler could only be done with an FPGA miceblue425 43:39. In 2020 he said putting the WTA on a PC "would degrade SQ" Head-Fi, Nov 2020.

In October 2026 he answered whether a chip DAC fed a perfect 768 kHz filter would match his designs. It would sound better, he said, but on whether it would match "one of my FPGA implementations to do the actual DAC itself? Absolutely not", because transient reconstruction must continue up to 104 MHz in his designs Part-Time Audiophile 35:47.

Reason 3: discrete conversion and the analog side

He stresses that the FPGA itself is not the DAC: "It's an FPGA DAC , but the FPGA is not the DAC" (2022) MFG Audio Reviews 13:14; the conversion is done by "individual flip flops, individual reference supplies and resistors" Darko.Audio 12:12. His case against on-chip conversion has stayed the same since 2014:

• Substrate noise. Digital switching noise couples through the shared silicon substrate into the analog section. On chips, he says, the fixes (triple well isolation, dedicated analog clock trees, manual layout) are "always an issue of mitigating the problem, never solving it" (2019) Head-Fi, May 2019. He repeated this in 2018, 2023, the Munich-show interview (likely May 2024, published February 2025) and 2026 Pursuit Perfect System 14:47The Headphone Show 6:58audio-2G 2:10HiFi Buys 30:47. In that Munich-show interview: "So, a chip-based DAC has fundamental problems that is impossible to resolve" audio-2G 2:10.
• Non-linear on-chip parts. On-chip resistors and capacitors are non-linear, which he says creates distortion, while discrete passives avoid it Head-Fi, Jul 2014RMAF 29:34HiFi Buys 31:32.
• The reference voltage. A chip's reference is buried inside it and is noisy and high in impedance; the differential structure used to cancel that noise works only for small signals, which he names as a source of noise floor modulation. Discrete designs let him build his own low-noise, low-impedance reference Head-Fi, Aug 2016Head-Fi, Dec 2018RMAF 30:26RMAF 31:09.
• A simpler analog path. Because chips must be differential to cancel substrate noise, they need several I-to-V and differential stages; his discrete DACs can run single-ended with one output stage Head-Fi, Aug 2014Head-Fi, Jul 2015Audiophilesdoteu 3:07. In 2015: "In DAC design, going balanced is essential with silicon design; there is simply too much substrate noise and other effects not too" Head-Fi, Jul 2015.

He links these choices to his claim of no measurable noise floor modulation, saying "chip DACs all have very large measurable noise floor modulation; all my DACs have none" (2019) Head-Fi, May 2019Darko.Audio 12:12.

Why not a custom ASIC for Chord

His answer has been consistent from 2014 to 2023. In 2020: "A custom chip would also consume a huge amount of time, and it's difficult to see how a business case could be made for the audiophile market" Head-Fi, Nov 2020. In February 2021, in a reply whose question is not preserved in this archive (the post does not name the design it discusses replacing with silicon), he said a 130 nm version would cost about 1M USD and a 13 nm one about 100M USD, and "To maintain SQ and the measurements you would need to keep the discrete flip-flop analogue conversion, so costs of implementation would still be high" Head-Fi, Feb 2021. In December 2023 he said the semiconductor companies he worked with had "zero interest in a high end DAC chip as the numbers are too small", and that an M Scaler WTA ASIC would be about a 2M USD project: "You would never sell enough to justify the NRE cost" Head-Fi, Dec 2023. He also wrote in 2019 that "I would only do a chip design for high volume non high end applications" Head-Fi, May 2019. He notes his Verilog code is the same for an ASIC or an FPGA, so the language is no barrier Head-Fi, Aug 2014Head-Fi, Jun 2018The Source AV 4:47.

The downsides he admits

• Cost and dependence on FPGA progress. "Now the down side to FPGA is that you are dependent on the FPGA performance" (2014), and the unit cost is higher Head-Fi, Apr 2014Audiophilesdoteu 1:31.
• Difficulty. In 2014 he called FPGA DAC design "at least an order of magnitude more difficult than simply using another audio chip to produce a boutique DAC", warned of "poorly measuring FPGA based garbage", and conceded "At least a chip based design will, at the DAC core, be competently designed, thoroughly reviewed and tested" Head-Fi, Aug 2014. In 2017 he said again that chip DACs are "competently designed, with good measurements" Head-Fi, Oct 2017.
• Dependence on FPGA progress since 2019. In January 2019 he was "less optimistic" about bringing M scaling to lower prices because "cost per gate as process is shrinking is actually increasing" Head-Fi, Jan 2019. In a post dated between March 2025 and March 2026 he wrote that "sadly FPGA developments have been way slower than I expected", with no cost-comparable replacement yet for the 28 nm 200T used in the Hugo M Scaler and Quartet Head-Fi, Mar 2025.
• Speed and power. In 2026: "disadvantages with FPGAs in that they're slower, power consumption is higher", though he said they still beat a microprocessor HiFi Buys 32:15. Hugo 2's FPGA draws about 800 mW (2017) Head-Fi, Mar 2017. His 2014 comparison ran the other way: he said there are "considerable benefits in FPGA in terms of power", since the FPGA uses a 28 nm process rather than a typical 180 nm mixed-signal process, with routing and timing closure as the FPGA's downside Head-Fi, Aug 2014. Power is what stands in the way of a pocket M Scaler: in 2017 he said "we need at least a tenfold improvement in power dissipation" Head-Fi, Oct 2017, and in 2020 that a Hugo with a built-in M Scaler was "an order of magnitude away" on power and cost Head-Fi, Nov 2020.
• Isolation is not total. In an interview published December 2019 (recording date not stated), describing the split between FPGA and discrete parts: "Well, not completely, but you can isolate the two domains from one another" Passion for Sound 17:00. In 2023 he gave FPGA noise as the reason the M scalers are separate units: "the noise that the FPGA generates must be kept away from the DAC part" Head-Fi, Mar 2023.

By 2020 he no longer saw gate count as a limit: "Currently, I have the capability to do anything I could possibly dream of doing from existing FPGAs if you are not too concerned about costs or power dissipation" Head-Fi, Nov 2020. In 2024 he described his approach as adding more large FPGAs in parallel, "as currently this is the only economic way of doing it" Head-Fi, Jan 2024.

What he has not said

Asked by Porta-Fi in 2018 about FPGA weaknesses article, Apr 2018, he said "I would like to think of it as challenges" and answered with the growth in tap counts from DAC64 to Blu MkII rather than naming a weakness article, Apr 2018. He gives no figures for what Chord's FPGAs cost per unit. Apart from the ESS9038 Pro tap count Head-Fi, Sep 2023, he gives no measured comparisons with specific named DAC chips in this material, and in 2016 he said Head-Fi's trade rules limit what he can say about competitors' products Head-Fi, Sep 2016.

Quotes

“Now silicon chip design means very high initial cost, so you go for big volume. But FPGA design means higher cost per device, but a great deal more flexibility.”2014-04-16 Head-Fi, Apr 2014

“I am committed to getting the best sound possible – and that is only achievable with FPGA’s and discrete DAC’s.”2017-12-09 article, Dec 2017

“In a discrete DAC the analogue parts are completely separate, with their own PSUs and drivers. So it's possible to fully isolate the analogue from the noisy digital sections.”2019-05-11 Head-Fi, May 2019

“A custom chip would also consume a huge amount of time, and it's difficult to see how a business case could be made for the audiophile market.”2020-11-12 Head-Fi, Nov 2020

Dated positions

Caveats and open points

• Several figures come from talks and interviews: Mojo's 500x processing claim, the FPGA's 740 DSP cores, the $10 million and five-cent die story, the three kilo-ohm substrate figure and the 104 MHz rate. Readers should check them against the recordings.
• He has given different start dates for his FPGA work (mid-1990s, 1992 and 1995) in different sources.
• Cost figures for ASIC masks and projects (1M and 100M USD in 2021, 2M USD in 2023) come from different years and process nodes, so they are not directly comparable.
• Claims that chip DACs measure worse are his own and are not independently verified here.
• Head-Fi, Mar 2025 has no exact date; the archive places it between 2025-03-27 and the 2026-03-03 scrape.

Topics: FPGA implementation and processing hardware, Other DAC architectures (R2R, delta-sigma, chips, 1-bit)